1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming replacement fins for a FinFET device using a targeted thickness for a patterned fin etch mask.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speeds of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of trenches 13, three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. An insulating material 17, e.g., silicon dioxide, provides electrical isolation between the fins 14 and effectively determines the final active fin height. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
In the FinFET device 10, the gate structure 16 encloses both sides and the upper surface of all or a portion of the fins 14 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins 14 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects and off-state leakage. When an appropriate voltage is applied to the gate electrode 16 of a FinFET device 10, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. Device designers are currently investigating alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices, which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
FIG. 1B is a perspective view of an illustrative prior art FinFET semiconductor device 10, wherein the overall fin structure of the device includes a substrate fin portion 14A and an alternative fin material portion or replacement fin 14B. As with the case above, the substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate, and the replacement fin 14B may be made of a material other than the substrate material, for example, silicon-germanium. As noted above, the use of such alternative fin materials improves the mobility of charge carriers in the device.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is non-trivial due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to FIG. 1B, the lattice constant of the replacement fin 14B may be substantially greater than the lattice constant of the substrate fin portion 14A of the fin 14. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the replacement fin 14B. As used herein, a “defect” essentially refers to a misfit dislocation at the interface between the substrate fin portion 14A and the replacement fin 14B or threading dislocations that propagate through the replacement fin 14B at well-defined angles corresponding to the (111) plane.
One of the proposed approaches for the formation of replacement fins 14B comprised of alternative materials for FinFET devices will now be discussed with reference to FIGS. 1C-1I, which are cross-sectional views of the fins taken in a gate width direction of the device 10. As shown in FIG. 1C, the initial substrate fin structures 14 are formed in the substrate 12 by performing an etching process through a patterned etch mask 15. FIG. 1D depicts the device 10 after the layer of insulating material 17 was deposited in the trenches 13, after a relatively high temperature anneal process (e.g., 900° C.+) was performed so as to densify the insulating material 17 and one or more CMP processes were performed to remove the etch mask 15 and excess amounts of the layer of insulating material 17. These operations expose the upper surface of the fins 14. Silicon dioxide is frequently used as the material for the layer of insulating material 17. Silicon dioxide has a linear coefficient of thermal expansion (CTE) of about 0.5 (E-6/° K) whereas a silicon substrate has a CTE of about 2.6 (E-6/° K). The difference in the CTEs of the materials causes a compressive force 17X to be exerted on the substrate fins 14 when the local oxide fill material 17 is annealed.
Next, as shown in FIG. 1E, a timed recessing etching process is performed to remove an upper portion of the initial substrate fins 14 (now denoted as fins 14A) such that they have a recessed upper surface 14R. The removal of a portion of fins 14 results in the formation of a plurality of replacement fin cavities 19 that are defined, at least partially, by the insulating material 17. FIG. 1E depicts an idealized situation wherein the shape of the replacement fin cavity 19 corresponds approximately to that of the removed portion of the substrate fin 14. However, that is not the case in at least some real-world applications. As shown in FIG. 1F, in practice, once the upper portions of the substrate fins 14 are removed, the insulating material 17 tends to expand, thereby reducing the size of the original fin cavities 19, that have been renumbered 19A to reflect this change in configuration. The insulating material 17 expands in an effort to reduce the compressive force 17X that was present in the layer of material 17 when it was formed in the trenches 13, annealed and restrained by the original substrate fins 14 (prior to the removal of the upper portion of the substrate fin 14). FIG. 1G is a SEM photograph showing the configuration of the modified fin cavities 19A after the upper portion of the substrate fin 14 is removed.
As shown in FIG. 1H, the replacement fins 14B that are formed in these modified fin cavities 19A will also have a cross-sectional configuration that corresponds approximately to the cross-sectional configuration of the modified fin cavities 19A, which is an undesirable profile for the replacement fin 14B. The replacement fin material 14B is grown on the recessed fin structures 14A by performing a selective epitaxial deposition process. The replacement fin 14B may be comprised of a variety of materials, e.g., SiGe0.25 (CTE of about 3.4), Ge (CTE of about 5.8), etc. Due to the mismatch between the CTEs of the insulating material 17 (e.g., silicon dioxide with a CTE of about 0.5) and the replacement fin 14B material (e.g., SiGe0.25 with a CTE of about 3.4), an unacceptable number of defects or faults may be formed in the replacement fin 14B during the epitaxial deposition process and the subsequent cool down.
FIG. 1I is a SEM photograph that shows the formation of the angled stacking faults or defects 21 in the replacement fin 14B. The angled stacking faults or defects 21 appear to originate at the interface between the replacement fin 14B and the insulating material 17. In this example, substrate fin 14A is made of silicon, the replacement fin 14B is made of SiGe0.25 and the layer of insulating material 17 is a HARP silicon dioxide. The formation of such defects or faults 21 makes the replacement fin 14B less desirable from a performance point of view.
The present disclosure is directed to various methods of forming replacement fins for a FinFET device using a targeted thickness for a patterned fin etch mask that may solve or reduce one or more of the problems identified above.